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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a dual/quad low power, high speed jfet operational amplifiers op282/OP482 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 general description the op282/OP482 dual and quad operational amplifiers feature excellent speed at exceptionally low supply currents. slew rate exceeds 7 v/ m s with supply current under 250 m a per amplifier. these unity gain stable amplifiers have a typical gain bandwidth of 4 mhz. the jfet input stage of the op282/OP482 insures bias current is typically a few picoamps and below 500 pa over the full temperature range. offset voltage is under 3 mv for the dual and under 4 mv for the quad. with a wide output swing, within 1.5 volts of each supply, low power consumption and high slew rate, the op282/OP482 are ideal for battery-powered systems or power restricted applica- tions. an input common-mode range that includes the positive supply makes the op282/OP482 an excellent choice for high- side signal conditioning. the op282/OP482 are specified over the extended industrial temperature range. both dual and quad amplifiers are available in plastic and ceramic dip plus soic surface mount packages. features high slew rate: 9 v/ m s wide bandwidth: 4 mhz low supply current: 250 m a/amplifier low offset voltage: 3 mv low bias current: 100 pa fast settling time common-mode range includes v+ unity gain stable applications active filters fast amplifiers integrators supply current monitoring pin connections 8-lead narrow-body soic 8-lead epoxy dip (s suffix) (p suffix) 1 2 3 45 6 7 8 out a ?n a +in a v op-482 v+ out b ?n b +in b op282 out a ?n a +in a v v+ out b ?n b +in b 1 2 3 4 5 6 7 8 op282 14-lead epoxy dip 14-lead narrow-body soic (p suffix) (s suffix) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 out a ?n a +in a v+ +in b ?n b out b out b ?n d +in d v +in c ?n c out c OP482 1 2 3 4 5 6 7 14 13 12 11 10 9 8 out a ?n a +in a v+ +in b ?n b out b out d ?n d +in d v +in c ?n c out c OP482
C2C op282/OP482Cspecifications electrical characteristics (@ v s = 6 15.0 v, t a = +25 8 c unless otherwise noted) parameter symbol conditions min typ max units input characteristics offset voltage v os op282 0.2 3 mv op282, C40 t a +85 c 4.5 mv offset voltage v os OP482 0.2 4 mv OP482, C40 t a +85 c6mv input bias current i b v cm = 0 v 3 100 pa v cm = 0 v, note 1 500 pa input offset current i os v cm = 0 v 1 50 pa v cm = 0 v, note 1 250 pa input voltage range C11 +15 v common-mode rejection cmr C11 v v cm +15 v, C40 t a +85 c7090 db large signal voltage gain a vo r l = 10 k w 20 v/mv r l = 10 k w , C40 t a +85 c 15 v/mv offset voltage drift d v os / d t10 m v/ c bias current drift d i b / d t 8 pa/ c output characteristics output voltage swing v o r l = 10 k w C13.5 13.9 13.5 v short circuit limit i sc source 3 10 ma sink C8 C12 ma open-loop output impedance z out f = 1 mhz 200 w power supply power supply rejection ratio psrr v s = 4.5 v to 18 v, C40 t a +85 c 25 316 m v/v supply current/amplifier i sy v o = 0 v, 40 t a +85 c 210 250 m a supply voltage range v s 4.5 18 v dynamic performance slew rate sr r l = 10 k w 79 v/ m s full-power bandwidth bw p 1% distortion 125 khz settling time t s to 0.01% 1.6 m s gain bandwidth product gbp 4 mhz phase margin ? o 55 degrees noise performance voltage noise e n p-p 0.1 hz to 10 hz 1.3 m v p-p voltage noise density e n f = 1 khz 36 nv/ ? hz current noise density i n 0.01 pa/ ? hz note 1 the input bias and offset currents are tested at t a = t j = +85 c. bias and offset currents are guaranteed but not tested at C40 c. specifications subject to change without notice. wafer test limits (@ v s = 6 15.0 v, t a = +25 8 c unless otherwise noted) parameter symbol conditions limit units offset voltage v os op282 3 mv max offset voltage v os OP482 4 mv max input bias current i b v cm = 0 v 100 pa max input offset current i os v cm = 0 v 50 pa max input voltage range 1 C11, +15 v min/max common-mode rejection cmrr C11 v v cm +15 v 70 db min power supply rejection ratio psrr v = 4.5 v to 18 v 316 m v/v large signal voltage gain a vo r l = 10 k w 20 v/mv min output voltage range v o r l = 10 k w 13.5 v min supply current/amplifier i sy v o = 0 v, r l = 250 m a max notes electrical tests and wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. 1 guaranteed by cmr test. specifications subject to change without notice. rev. b
op282/OP482 rev. b C3C absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v input voltage 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v differential input voltage 1 . . . . . . . . . . . . . . . . . . . . . . . 36 v output short-circuit duration . . . . . . . . . . . . . . . . indefinite storage temperature range p, s packages . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c operating temperature range op282a, OP482a . . . . . . . . . . . . . . . . . . C55 c to +125 c op282g, OP482g . . . . . . . . . . . . . . . . . . . C40 c to +85 c junction temperature range p, s packages . . . . . . . . . . . . . . . . . . . . . . C65 c to +125 c lead temperature range (soldering, 60 sec) . . . . . . +300 c package type u ja 2 u jc units 8-pin plastic dip (p) 103 43 c/w 8-pin soic (s) 158 43 c/w 14-pin plastic dip (p) 83 39 c/w 14-pin soic (s) 120 36 c/w notes 1 for supply voltages less than 18 v, the absolute maximum input voltage is equal to the supply voltage. 2 q ja is specified for the worst case conditions, i.e., q ja is specified for device in socket for cerdip, p-dip; q ja is specified for device soldered in circuit board for soic package. ordering guide temperature package package model range description option op282gp C40 c to +85 c 8-pin plastic dip n-8 op282gs C40 c to +85 c 8-pin soic so-8 OP482gp C40 c to +85 c 14-pin plastic dip n-14 OP482gs C40 c to +85 c 14-pin soic so-14 dice characteristics op282 die size 0.063 3 0.060 inch, 3,780 sq. mils OP482 die size 0.070 3 0.098 inch, 6,860 sq. mils
op282/OP482 rev. b C4C applications information the op282 and OP482 are single and dual jfet op amps that have been optimized for high speed at low power. this combination makes these amplifiers excellent choices for battery powered or low power applications requiring above average performance. applications benefiting from this performance combination include telecom, geophysical exploration, portable medical equipment and navigational instrumentation. high side signal conditioning there are many applications that require the sensing of signals near the positive rail. op282s and OP482s have been tested and guaranteed over a common-mode range (C11 v v cm +15 v) that includes the positive supply. one application where this is commonly used is in the sensing of power supply currents. this enables it to be used in current sensing applications such as the partial circuit shown in figure 1. in this circuit, the voltage drop across a low value resistor, such as the 0.1 w shown here, is amplified and compared to 7.5 volts. the output can then be used for current limiting. +15v 100k 100k 100k 500k 0.1 1/2 op282 + r l w figure 1. phase inversion phase inversion most jfet-input amplifiers will invert the phase of the input signal if either input exceeds the input common-mode range. for the op282 and OP482 negative signals in excess of approxi- mately 14 volts will cause phase inversion. the cause of this effect is saturation of the input stage leading to the forward- biasing of a drain-gate diode. a simple fix for this in noninverting applications is to place a resistor in series with the noninverting input. this limits the amount of current through the forward- biased diode and prevents the shutting down of the output stage. for the op282/OP482, a value of 200 k w has been found to work. however, this adds a significant amount of noise. -15 15 10 5 0 -5 -10 -15 -10 -5 0 5 10 15 v in out v figure 2. op282 phase reversal active filters the op282 and OP482s wide bandwidth and high slew rates make either an excellent choice for many filter applications. there are many types of active filter configurations, but the four most popular configurations are butterworth, elliptical, bessel, and chebyshev. each type has a response that is optimized for a given characteristic as shown in table i. programmable state-variable filter table i. amplitude amplitude type selectivity overshoot phase (pass band) (stop band) butterworth moderate good max flat chebyshev good moderate nonlinear equal ripple elliptical best poor equal ripple equal ripple bessel (thompson) poor best linear
op282/OP482 rev. b C5C the circuit shown in figure 3 can be used to accurately program the q, the cutoff frequency f c , and the gain of a two pole state-variable filter. OP482s have been used in this design because of their high bandwidths, low power and low noise. this circuit takes only three packages to build because of the quad configuration of the op amps and dacs. the dacs shown are all used in the voltage mode so all values are dependent only on the accuracy of the dac and not on the absolute values of the dacs resistive ladders. this make this circuit unusually accurate for a programmable filter. adjusting dac 1 changes the signal amplitude across r1; therefore, the dac attenuation times r1 determines the amount of signal current that charges the integrating capacitor, c1. this cutoff frequency can now be expressed as: fc = 1 2 p r 1 c 1 d 1 256 ? ? ? ? where d 1 is the digital code for the dac. gain of this circuit is set by adjusting d 3 . the gain equation is: gain = r 4 r 5 d 3 256 ? ? ? ? dac 2 is used to set the q of the circuit. adjusting this dac controls the amount of feedback from the bandpass node to the input summing node. note that the digital value of the dac is in the numerator, therefore zero code is not a valid operating point. q = r 2 r 3 256 d 2 ? ? ? ? r5 2k 1/4 OP482 - + low pass r6 2k r7 2k bandpass r1 2k 1/4 OP482 - + v in 1/4 dac8408 r4 2k 1/4 dac8408 1/4 OP482 - + 1/4 OP482 - + high pass 1/4 dac8408 - + 1/4 OP482 r1 2k 1/4 dac8408 1/4 OP482 - + 1/4 OP482 - + r2 1k r3 2k 1/4 OP482 - + c1 1000pf c1 1000pf figure 3.
op282/OP482 rev. b C6C op282/OP482 spice macro model figure 4 shows the op282 spice macro model. the model for the OP482 is similar to that of the op282, but there are some minor changes in the circuit values. contact adi for a copy of the latest spice model diskette for both listings. in- in+ cin r1 r2 ios 3 j1 j2 56 c2 r3 r4 50 eos i1 99 4 7 g1 9 v2 d1 r5 c3 98 eref v3 d2 8 c4 11 e2 r6 r7 98 13 12 r8 g2 14 19 g3 g11 20 c5 c6 c13 r21 r9 r19 21 e13 c14 27 g17 d7 g18 28 d8 d3 25 26 d4 d5 d6 v4 v5 g19 g20 isy r25 24 23 c15 r23 g15 98 r26 r27 29 r28 l5 30 vout 50 99 r22 2 1 10 figure 4.
op282/OP482 rev. b C7C op282 spice macro model * node assignments * noninverting input * inverting input * positive supply * negative supply * output * .subckt op282 1 2 99 50 30 * * input stage & pole at 15 mhz * r1 1 3 5e11 r2 2 3 5e11 r3 5 50 3871.3 r4 6 50 3871.3 cin 1 2 5e-12 c2 5 6 1.37e-12 i1 99 4 0.1e-3 ios 1 2 5e-13 eos 7 1 poly(1) 21 24 200e-6 1 j1 524 jx j2 674 jx * eref 98 0 24 0 1 * * gain stage & pole at 124 hz * r5 9 98 1.16e8 c3 9 98 1.11e-11 g1 98 9 5 6 2.58e-4 v2 99 8 1.2 v3 10 50 1.2 d1 98dx d2 10 9 dx * * negative zero at 4 mhz * r6 11 12 1e6 r7 12 98 1 c4 11 12 39.8e-15 e2 11 98 9 24 1e6 * * pole at 15 mhz * r8 13 98 1e6 c5 13 98 10.6e-15 g2 98 13 12 24 1e-6 * * pole at 15 mhz * r9 14 98 1e6 c6 14 98 10.6e-15 g3 98 14 13 24 1e-6 * * pole at 15 mhz * r19 19 98 1e6 c13 19 98 10.6e-15 g11 98 19 14 24 1e-6 * * common-mode gain network with zero at 11 khz * r21 20 21 1e6 r22 21 98 1 c14 20 21 14.38e-12 e13 98 20 3 24 31.62 * * pole at 15 mhz * r23 23 98 1e6 c15 23 98 10.6e-15 g15 98 23 19 24 1e-6 * * output stage * r25 24 99 5e6 r26 24 50 5e6 isy 99 50 107e-6 r27 29 99 700 r28 29 50 700 l5 29 30 1e-8 g17 27 50 23 29 1.43e-3 g18 28 50 29 23 1.43e-3 g19 29 99 99 23 1.43e-3 g20 50 29 23 50 1.43e-3 v4 25 29 2.8 v5 29 26 3.5 d3 23 25 dx d4 26 23 dx d5 99 27 dx d6 99 28 dx d7 50 27 dy d8 50 28 dy * * models used * .model jx pjf(beta = 3.34e-4 vto = C2.000 is = 3e-12) .model dx d(is = 1e-15) .model dy d(is = 1e-15 bv = 50) .ends op282
op282/OP482 rev. b C8C frequency ?hz 1k 10k 100k 1m 100m 10m 0 40 20 80 60 open-loop gain ?db phase ?degrees 90 135 0 45 180 v s = ?5v t a = +25 c figure 5. open-loop gain, phase vs. frequency frequency ?hz 1m 1k 10k 100k 100m 10m a = +100 vcl a = +1 vcl a = +10 vcl closed-loop gain ?db 10 30 20 40 50 60 0 ?0 ?0 v s = ?5v t a = +25 c figure 6. closed-loop gain vs. frequency 60 45 40 55 50 phase margin ?degrees 125 ?5 ?5 ?0 25 0 50 75 100 temperature ?? v = ?5v s r l = 10k gbw m 50 3.5 3.0 4.5 4.0 gain bandwidth product ?mh z figure 7. OP482 phase margin and gain bandwidth product vs. temperature overshoot ?% 500 0 300 100 200 400 load capacitance ?pf 70 10 0 60 50 40 30 20 a vcl = +1 negative edge l positive edge v s = ?5v r l = 2k v in = 100mv p-p a vcl = +1 w figure 11. small signal overshoot vs. load capacitance 1000 1.0 0.1 100 10 input bias current ?pa temperature ?? 125 ?5 ?0 25 0 50 75 100 v cm = 0 v s = ?5v figure 12. op282 input bias current vs. temperature common - mode voltage ?v 15 ?5 0 510 ?0 ? t a = +25 c v s = ?5v input bias current ?pa 100 1 1000 0.1 10 figure 13. op282 input bias current vs. common-mode voltage 125 ?5 ?5 ?0 25 0 50 75 100 temperature ?? open-loop gain ?v/mv 30 35 20 15 5 25 10 v = ?5v s r l = 10k figure 8. open-loop gain (v/mv) slew rate ?v/? 20 25 15 10 5 l 125 ?5 ?5 ?0 25 0 50 75 100 temperature c ?sr + sr v s = ?5v r l = 10k c l = 50pf figure 9. op282/OP482 slew rate vs. temperature frequency ?hz 10 100 1k 10k 80 0 20 10 40 30 50 60 70 voltage noise density ?nv/ hz v = ?5v s t = +25? a figure 10. voltage noise density vs. frequency
op282/OP482 rev. b C9C supply voltage ?volts ?5 0 ?0 ?0 ? relative supply current ?isy 1.10 0.90 1.15 0.85 1.00 1.05 0.95 t a = +25? figure 14. relative supply current vs. supply voltage relative supply current ?isy temperature ?? 1.20 0.80 0.90 0.85 1.00 0.95 1.05 1.10 1.15 ?0 ?5 125 100 75 50 25 0 ?5 v sup = ?5 figure 15. relative supply current vs. temperature short circuit current ?ma 20 15 5 10 v s = ?5v sink source temperature ?? 75 ?5 0 25 50 ?0 ?5 100 125 figure 16. op282/OP482 short circuit current vs. temperature supply voltage ?volts ?5 0 ?0 ? ?0 ? output voltage swing ?volts 0 15 5 10 20 ?0 ?0 ?5 r l = 10k t a = +25? w figure 17. output voltage swing vs. supply voltage load resistance ? w 10k 1k 100 absolute output voltage ?volts 16 0 2 8 6 10 12 14 4 t a = +25? v s = ?5v positive swing negative swing figure 18. maximum output voltage vs. load resistance maximum output swing ?volts 30 0 15 5 10 25 20 v s = ?5v t a = +25? r l = 10k a vcl = +1 100k 10k 1k 1m frequency ?hz w figure 19. maximum output swing vs. frequency impedance ? w 600 0 300 100 200 500 400 v s = ?5v t a = +25 c a = 1000 vcl a = 100 vcl a = +10 vcl a = 1 vcl 1m 1k 100 100k 10k frequency ?hz figure 20. OP482 closed-loop out- put impedance vs. frequency psrr ?db 100 ?0 40 0 20 80 60 1m 1k 100 100k 10k t a = +25 c v s = ?5v v = 100mv frequency ?hz + psrr ?psrr d figure 21. op282 power supply rejection ratio (psrr) vs. frequency cmrr ?db 100 ?0 40 0 20 80 60 1m 1k 100 100k 10k frequency ?hz t a = +25 c v = ?5v s v = 100mv cm figure 22. op282 common-mode rejection ratio (cmrr) vs. frequency
op282/OP482 rev. b C10C 0 units 280 120 40 80 240 160 200 2000 -1600 -2000 1600 1200 800 400 0 -400 -800 -1200 v ?? os v = ?5v s t = +25? a (630 op amps ) 315 op282 figure 23. v os distribution "p" package 0 units 280 120 40 80 240 160 200 2000 ?600 ?000 1600 1200 800 400 0 ?00 ?00 ?200 v ?? os v s = ?5v t a = +25 c (640 op amps) 320 op282 figure 24. v os distribution "z" package units 0 600 700 300 100 200 400 500 32 4 0 28 24 20 16 12 8 tcv ??/? os 1200 op amps v s = ?5v -40? t a +125 c 300 OP482 figure 27. OP482 tcv os distribution "z" package units 0 600 700 300 100 200 400 500 32 4 0 28 24 20 16 12 8 tcv ??/? os 1200 op amps v s = ?5v -40? t a +85 c 300 OP482 figure 28. tcv os distribution "p" package units 320 0 80 40 160 120 200 240 280 32 4 0 28 24 20 16 12 8 tcv ??/? os figure 25. op282 tcv os ( m v/ c) distribution "p" package units 320 0 80 40 160 120 200 240 280 32 4 0 28 24 20 16 12 8 tcv ??/? os figure 26. op282 tcv os ( m v/ c) distribution "z" package units 0 600 700 300 100 200 400 500 2000 ?600 ?000 1600 1200 800 400 0 ?00 ?00 ?200 v ?? os t a = +25 c v s = ?5v 1200 op amps 300 3 OP482 figure 30. OP482 v os distribution p package v ?? os 2000 ?600 ?000 1600 1200 800 400 0 ?00 ?00 ?200 units 0 600 700 300 100 200 400 500 t a = +25 c v s = ?5v 1200 op amps 300 3 OP482 figure 29. OP482 v os distribution z package
op282/OP482 rev. b C11C outline dimensions dimensions shown in inches and (mm). 8-lead narrow-body soic (s suffix) 14-lead narrow-body soic (s suffix) 8-lead epoxy dip (p suffix) 14-lead epoxy dip (p suffix) 20-position chip carrier (rc suffix)
c1597C24C11/91 printed in u.s.a. C12C rev. b

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